Progress Report from 25/01/2016 to 15/02/2016
– Release of the project’s source-code;
– Writing of the Dissertations’ article;
– Preparation of a slide presentation for the final presentation;
– Final presentation and discussion.
Progress Report from 28/12/2015 to 25/01/2016
– Writing of the Dissertation Report;
– Final Tests & Measurements;
– Review of the Dissertation Report;
Progress Report from 07/11/2015 to 21/12/2015
– Review of the Verilog code and Matlab scripts for both the Ranging and Transceiver configurations.
– Initialize the writing of the Dissertation Report.
Progress Report from 30/11/2015 to 07/12/2015
– Modify the boards in order to test different impedance matching configurations: 1 board configured for driver strength and other board in a Series Termination Scheme;
– Testing of the performance of both boards in the Ranging and Transceiver configurations.
Progress Report from 23/11/2015 to 30/11/2015
– Develop Matlab scripts for testing the payload error-rate of data exchanged between boards in the Transceiver configuration;
– Attempt to minimize pulse-lengths on both the Ranging and Transceiver configuration by exploring the maximum switching rates of the FPGA’s I/O pins and internal logic’s limitations.
Progress Report from 16/11/2015 to 23/11/2015
– Prepare additional boards for the Transceiver configuration;
– Testing of the Transceiver configuration on actual hardware.
Progress Report from 9/11/2015 to 16/11/2015
– Initialize the development of the Transceiver configuration in Verilog;
– Initialize the Functional (RTL) simulation of the Transceiver functionality.
Progress Report from 2/11/2015 to 9/11/2015
– Testing of N=31 bit Gold sequences in Ranging configuration;
– Initialize the development of a Transceiver architecture based on the same TX/RX modules used in the Ranging configuration;
– Study of Kasami Sequences for the Ranging and Transceiver configuration.
Progress Report from 26/10/2015 to 2/11/2015
– Initialize the development of a Matlab script for processing Ranging measurements;
– Prepare a board and required hardware for Ranging measurements;
– Testing of the Ranging configuration with a transmission line.
Progress Report from 19/10/2015 to 26/10/2015
– Initialize the development of the RX module in Verilog for the Ranging configuration;
– Initialize the Functional (RTL) simulation of the Ranging measurements functionality (echo detection using transmission lines).