The solution is based on IR-UWB and Continuous-Time Binary-Value (CTBV) signal processing, as described per [2, 3], in which short-duration impulses in the nanosecond or picosecond range translate into the utilisation of a large portion of radio spectrum. This is a lower data-rate solution but also lower-power and less complex, therefore consuming fewer logic resources, as opposed to Multi-carrier Ultra-WideBand (M-UWB) options such as Multi-Band Orthogonal Frequency-Division Multiplexing (MB-OFDM) implementations. The proposed approach for the dissertation work is based on the strategy introduced by Professor Tor Sverre Land in [1]. The principles of implementation will be very similar, but the methodology differs in the physical implementation of the system as no custom CMOS chip will be used for the RF front-end or PN correlation. Because the work also focused on obtaining data from testing the design on real hardware, one of the main challenges of the project was managing the variability of propagation delays between logic regions and working with the available speed ratings of the programmable gates, limitations even more relevant on low-budget FPGAs which have operational clock speeds in the range of a few hundreds of MHz.
Design Architecture
The IR-UWB system will be implemented using FPGAs with pulse generator (TX) and pulse detector (RX) modules working in a CTBV sampling scheme.
Selection of Hardware Parts and BoM restrictions
This project aim is to develop a lower-cost alternative to existing UWB systems, which may imply the selection of a low-cost FPGA model. It is also desired to limit the number of external components in the RF frontend by choosing to do as much of signal processing as possible in programmable logic. When compared to more expensive and high-end design approaches which make use of state-of-the-art ADCs and FPGAs, some performance loss is expected. But those high-end systems can impose a BoM in the several hundred Euros range, sometimes thousands of Euros for the FPGA boards alone such as the Xilinx Virtex-II XC2VP70 in [4].
FPGA board selection and software deployment
BoM budget restrictions mean that only relatively less expensive FPGAs can be used in the prototype. However, low-cost FPGAs typically have lower maximum operation frequencies of up to only few hundreds of MHz. But UWB systems do require fast sampling rates and, even with a clock frequency reduction scheme achievable with parallel computing, I/O timing constraints can still undermine system performance. As such, Low-end and Mid-range FPGA boards from Microsemi®, Xilinx® and Altera® have been considered. These include the models:
Altera Cyclone-II to Cyclone-V family, including the very low-budget Cyclone II EP2C5T144
Microsemi Proasic3 family, model A3PE1500 as recommended by Professor Sérgio Reis Cunha
Xilinx Spartan-6 family, model XC6SLX25T for its integrated DDR3 memory controllers and built-in high-speed transceivers.
Some performance specifications and other features under analysis include:
1. I/O timing constraints
2. Internal logic timing constraints
3. Maximum clock frequency
4. Price
5. Embedded fast and constant-delay shift-register logic (DDR memory, HDMI, PCI Express) as proposed by Professor José Carlos dos Santos Alves
6. DSP capabilities and built-in Radio Transceivers
7. Number of Logical Elements
8. Power consumption
9. Applicable international export restrictions
References:
[1] Tor Sverre Lande. Impulse-based ultra-wide-band (uwb) radio systems and applications.
Available at https://www.youtube.com/watch?v=mqq9HrLqYJY, jun 2008.
[2] S. Sudalaiyandi, H.A. Hjortland, Tuan-Anh Vu, O. Naess, and T.S. Lande. Continuous-time
high-precision ir-uwb ranging-system in 90 nm cmos. In Solid State Circuits Conference
(A-SSCC), 2012 IEEE Asian, pages 349–352, Nov 2012.
[3] Tor Sverre Lande. Impulse-based ultra-wide-band (uwb) radio systems and applications.
Available at https://www.youtube.com/watch?v=mqq9HrLqYJY, jun 2008.
[4] D. Agarwal, C.R. Anderson, and P.M. Athanas. An 8 ghz ultra wideband transceiver prototyping
testbed. In Rapid System Prototyping, 2005. (RSP 2005). The 16th IEEE International
Workshop on, pages 121–127, June 2005 .
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