Week #3

Progress Report from 28/09/2015 to 05/10/2015

Completed Tasks:

-Modification of the initial Workplan: Verilog development, functional simulation and deployment of proof-of-concept implementations is scheduled to precede RF circuitry and Antenna development, which might or might not be included in the final work;

-Development of the TX module based on a chain of XOR stages and a Generator Polynomial (for generating a PN Sequence for transmission);

-Initiation of the functional (RTL) simulation of the TX module.