Progress Report from 9/11/2015 to 16/11/2015
Completed Tasks:
– Initialize the development of the Transceiver configuration in Verilog;
– Initialize the Functional (RTL) simulation of the Transceiver functionality.
MSc Dissertation by Tiago Costa at FEUP
Progress Report from 9/11/2015 to 16/11/2015
Completed Tasks:
– Initialize the development of the Transceiver configuration in Verilog;
– Initialize the Functional (RTL) simulation of the Transceiver functionality.