Week #5

Progress Report from 12/10/2015 to 19/10/2015

Completed Tasks:

– Study of Gold Sequences and experimentation with Gold Sequence generation algorithms;

– Initialize the development of an RX module architecture for ranging purposes with half pulse-length resolution;

– Initialize the Functional (RTL) simulation of the Ranging measurements functionality (echo detection using transmission lines);

– Development of a simple UART communication protocol between the FPGA hardware and an external control system (laptop) for ranging data logging and plotting.


Week #4

Progress Report from 05/10/2015 to 12/10/2015

Completed Tasks:

– 2nd meeting with Supervisor;

– Deployment of the TX module on FPGA hardware (Altera Cyclone II based board: EP2C5T144);

– Successful demonstration of the TX module functionality: detection of transmitted sequences on a 2nd board at a rate of approximately 3ns per bit (up to 17 bits per symbol, or 17 pulses per chip); Detection without the RX module based on logic comparators (combinational logic);

– Draft of a Ranging configuration scheme for the same FPGA hardware.

Week #3

Progress Report from 28/09/2015 to 05/10/2015

Completed Tasks:

-Modification of the initial Workplan: Verilog development, functional simulation and deployment of proof-of-concept implementations is scheduled to precede RF circuitry and Antenna development, which might or might not be included in the final work;

-Development of the TX module based on a chain of XOR stages and a Generator Polynomial (for generating a PN Sequence for transmission);

-Initiation of the functional (RTL) simulation of the TX module.

Week #1

Progress Report from 14/09/2015 to 21/09/2015

Completed Tasks:
– Deployment of the project’s website;
– Setup of Altera’s Quartus II IDE and Modelsim for Verilog development simulation.